Conventionally, for the purpose of drilling a hole through a multi-layered circuit board, there has been a technology of detecting the surface height of a spot to be machined and of drilling the hole to a specified depth based on the detected height as disclosed in Japanese Patent Laid-Open No. 2001-341052. This improves precision of the depth of the hole to be machined. However, because the thickness of the multi-layered circuit board varies, it was not always possible by this method to steadily form a blind hole for connecting upper and lower conductive layers.
Then, there has been provided a technology of providing a measuring area in each of the laminated conductive layers in advance, of exposing each measuring area before drilling a hole and of drilling the hole while confirming position of a tool in the height direction as disclosed in Japanese Patent Laid-Open No. 2004-63771. It allowed the blind hole for connecting upper and lower conductive layers to be steadily formed.
By the way, a power terminal (power pin), e.g., a pin, of an electronic part such as an IC package is connected with a desirable conductive layer as follows in mounting the IC package on the multi-layered circuit board. That is, a hole that reaches to the desirable conductive layer is drilled from the surface of the multi-layered substrate and plating is carried out to form a plating layer on an inner face of the hole. Then, the power terminal (pin) or the like is inserted into the hole and soldering is carried out to electrically connect the power terminal (pin) with the desirable conductive layer through an intermediary of the plated hole.
FIG. 4 is a section view of a conventional multi-layered circuit board.
The multi-layered circuit board 1 shown in the figure is formed as follows. That is, the multi-layered circuit board 1 is formed by laminating a third substrate 2 composed of a conductive layer 2a and an insulating layer 2b combined from each other, a second substrate 3 composed of conductive layers 3a and 3c and an insulating layer 3b combined from each other, a first substrate 4 composed of a conductive layer 4a and an insulating layer 4b combined from each other and a surface substrate 5 composed of a conductive layer 5a and an insulating layer 5b combined with each other in order by means of adhesive and by combining them with each other through heat treatment. Here, although circuit patterns are formed on the conductive layers 3a, 3c and 4a, i.e., the inner laminated layers, there are cases when circuit patterns are formed and when no circuit pattern is formed on the surface conductive layers 5a and the back conductive layer 2a. In the case of the second substrate 3, the conductive layer 3a is electrically connected with the conductive layer 3c′ through the intermediary of a plating layer 7 formed on a connecting hole 6 by plating.
Next, a hole 8 for connecting a power terminal of electronic parts, such as a pin, with a desirable conductive layer (the first conductive layer 4a in case of FIG. 4) is drilled from the side for mounting the electronic part such as an IC package (referred to as a surface side hereinafter). Still more, a connecting hole for connecting the surface conductive layer 5a and/or the back conductive layer 2a with the inner conductive layers 3a and 3c is drilled as necessary.
Then, a plating layer 9 is formed by plating the inner part of the power feeding connecting hole (not shown in FIG. 4) connecting the surface conductive layer 5a and/or the back conductive layer 2a with the inner conductive layers 3a and 3c immediately when the circuit patterns are formed on the conductive layer 5a on the surface side and on the conductive layer 2a on the back side opposite from the surface side or after forming the circuit patterns by etching when no circuit pattern is formed on the conductive layers 5a and 2a. 
Although the plating is normally carried out under sufficient control, there is a case when a thickness of the plating layer 9 at the bottom of the hole 8 becomes too thick or when a diameter of the plating layer 9 at the bottom of the hole 8 becomes small as compared to that at the entrance side as shown in the figure. When the plating layer 9 is formed, an end of the power terminal cannot be inserted to a desired depth and the electronic part comes up above the surface of the multi-layered circuit board 1. If the electronic part comes up above the multi-layered circuit board, the power terminal (pin) is apt to be damaged due to vibration and the like, reducing its reliability. Still more, there arises such a problem that if the external dimension of the multi-layered circuit board as a product incorporating electronic parts becomes large, it may not be stored within an electronic apparatus using the multi-layered circuit board.
In such a case, it is conceivable to avoid the dispersion or partial increase of the thickness of the plating layer by forming the hole 8 as a through hole. However, if this through hole is formed close to the circuit pattern on the back side, there is a case when the electronic part causes erroneous operation due to noise as a result of electro-magnetic effect that is caused by either one of them to the other. Accordingly, it is necessary to remove the unnecessary plating layer after plating when the hole 8 for positioning the power terminal is formed as the through hole.
However, it is not possible to remove the unnecessary plating layer accurately by the technology of Japanese Patent Laid-Open No. 2004-63771 because a tool electrically conducts with the desired conductive layer via the plating layer in removing the unnecessary plating layer.
Accordingly, it is an object of the invention to provide a multi-layered circuit board and a manufacturing method of the multi-layered circuit board that enables electronic parts to be adequately mounted and that will not hamper performance of the electronic parts.